AVS解码器在DSP平台上的优化  

AVS Decoder Optimization Based on DSP

作　　者：刘微[1] 李向荣[2] 

机构地区：[1]海信集团有限公司,山东青岛266071 [2]青岛科技大学机电学院,山东青岛266061

出　　处：《电子器件》2010年第1期132-134,共3页Chinese Journal of Electron Devices

基　　金："973"项目资助(2009CB320905);山东省博士后科研项目专项经费资助(200602009)

摘　　要：为在嵌入式DSP平台上提高AVS解码器的运行效率,提出一种基于L1P cache的优化方法。将程序代码划分为4个模块,每个模块容量均小于L1P的容量;并改变传统的针对单个宏块进行顺序处理的模式,使每个程序模块依次处理一个宏块行的数据,从而减少4×M×(N-1)次代码冲刷。实验结果表明,基于L1P Cache的方法提高了处理器读取程序代码的效率,使解码器速度提高20%。To enhance the running efficiency of AVS decoder in the embedded platform, an optimized method was proposed based on the L1P Cache, the program code is divided into 4 modules, the capacity of each module is smaller than the capacity of L1P. The traditional processing pattern by order aiming to single macroblock was changed to make every program module process washout can be reduced. The experiment result the data of one macroblock row in turn, thus 4× M ×（N - 1 ） code shows the method based on LIP Cache enhances the efficiency of processor reading procedure code, andmakes the decoder speed enhance 20%.

关 键 词：AVS CACHE 优化 解码器 

分 类 号：TN943[电子电信—信号与信息处理] TN919.81[电子电信—信息与通信工程]