基于FPGA的动态目标跟踪系统设计  

Moving target tracking system design based on FPGA

作　　者：吴长江[1] 赵不贿[1] 郑博[1] 于小燕[1] 

机构地区：[1]江苏大学电气信息工程学院,江苏镇江212013

出　　处：《电子技术应用》2010年第3期45-47,50,共4页Application of Electronic Technique

摘　　要：为了解决基于PC机的视频动态目标跟踪实时性瓶颈问题,设计出一种基于FPGA的动态目标跟踪系统。设计遵循图像处理金字塔模型,针对低层和中层算法简单、数据量大且存在一定并行性等特点采用FPGA硬件实现,而高层较复杂算法使用Nios Ⅱ软核进行C语言编程。整个设计采用Verilog-HDL对算法完成建模与实现,并在QUARTUS Ⅱ上进行了综合、布线等工作,最后以Altera公司的DE2开发板为硬件平台实现了整个系统。In order to overcome the bottleneck of real-time in moving target tracking system based on PC, this paper designs a moving target tracking system based on FPGA. This design uses the pyramid model of image processing. As low and middle-level algorithms are simple, the amounts of data are large and partially parallel, FPGA hardware implementation is adopted. Then more complex high-level algorithms use Nios II soft-core for C language programming to be resolved. The modeling and realization are achieved by Verilog-HDL , and synthesis and place＆route are completed in Quartus II software platform. Finally, this design implements on Ahera＇DE2 development and education board hardware platform.

关 键 词：FPGA 视觉跟踪 VERILOG-HDL 动态目标 NIOS II 

分 类 号：TN911.72[电子电信—通信与信息系统]