基于VHDL的TPC译码器设计  

Design of TPC Decoder Based on VHDL

作　　者：向冰[1] 

机构地区：[1]中国空空导弹研究院,河南洛阳471009

出　　处：《现代电子技术》2010年第7期73-76,共4页Modern Electronics Technique

摘　　要：Turbo乘积码是一种性能卓越的前向纠错码,具有译码复杂度低,且在低信噪比时可以获得近似最优的性能。介绍基于Chase算法的Turbo乘积码软入软出(SISO)迭代译码算法,提出基于VHDL硬件描述语言的TPC译码器设计方案,并在FPGA芯片上进行了仿真和验证。仿真结果证明该译码器有很大的实用性和灵活性。Turbo product code（TPC） is a kind of forward error correction codes with excellent performance.TPC has low decoding complexity and achieves near-optimum performances at low signal-to-noise ratio.The soft in soft out（SISO） iteration decoding algorithm for Turbo product code which is based on Chase algorithm and a method of hardware design for Turbo product code iterative decoder based on VHDL are introduced.The decoder is simulated and implemented on FPGA circuit.The simulation results prove that the decoder has functions of validity and feasibility.

关 键 词：TPC码 软判决译码 迭代译码 VHDL FPGA 

分 类 号：TN911.22[电子电信—通信与信息系统]