千兆比特数据率LVDS接口电路设计  

Design of LVDS Interface for Gb/s Operation

作　　者：矫逸书[1] 周玉梅[1] 蒋见花[1] 

机构地区：[1]中国科学院微电子学研究所,北京100029

出　　处：《固体电子学研究与进展》2010年第1期119-123,共5页Research & Progress of SSE

摘　　要：设计了一个采用0.18μm1.8V/3.3V CMOS工艺制造的千兆比特数据率LVDS I/O接口电路。发送器电路采用内部参考电流源和片上匹配电阻,使工艺偏差、温度变化对输出信号幅度的影响减小50%;接收器电路采用一种改进的结构,通过检测输入共模电平,自适应调整预放大器偏置电压,保证跨导Gm在LVDS标准[1]要求的共模范围内恒定,因此芯片在接收端引入的抖动最小。芯片面积0.175mm2,3.3V电源电压下功耗为33mW,测试表明此接口传输速率达到1Gb/s。This paper presents the design and the implementation of 1 Gb/s LVDS I/O interface in standard CMOS technology. By using an internal temperature independent current source and an integrated terminal resistor, the variation of LVDS signal amplitude caused by process deviation and temperature variation can be reduced 50M. The preamplifier of the receiver implements folded-cascode architecture, accompaned with an input common mode voltage detecting circuit. Thus, the input common mode voltage measurement range can satisfy the LVDS std. without using low threshold transistors. And the gain of the preamplifier keeps constant independent of the common mode voltage variations, which minimized the introduced jitter when the proposed transceiver works as a buffer. The test chip occupies 0. 175 mm^2 and exhibits a power consumption of 33 mW with 3.3 V supply voltage. Test indicates that the transceiver can operate up to 1 Gb/s.

关 键 词：低电压差分信号传输 高速接口 发送器 接收器 

分 类 号：TN432[电子电信—微电子学与固体电子学]