基于CMOS工艺V-NPN晶体管设计的用于接收机的双极型有源混频器  

A Bipolar Mixer for Low Frequency Receiver Using V-NPN Transistors in Deep N-well CMOS Technology

作　　者：张建恩[1,2] 华斯亮[1,2] 王东辉[1,2] 侯朝焕[1,2] 

机构地区：[1]中国科学院声学研究所 [2]中国科学院研究生院

出　　处：《微计算机应用》2010年第4期39-42,共4页Microcomputer Applications

摘　　要：随着声纳通信技术的发展,需要使用CMOS工艺设计用于声纳通信接收机中的低噪声低频混频器。由于MOSFETs的闪烁噪声拐角频率通常在几MHz,在低频工作时会有非常大的闪烁噪声。这使得用MOSFETs设计的传统CMOS有源混频器,在低频低噪声系统中不能使用。本文提出了使用深N阱CMOS工艺中的垂直寄生NPN晶体管(V-NPN)设计的双极型有源混频器。该垂直寄生NPN晶体管的闪烁噪声拐角频率通常为几KHz,因此可以用来设计低噪声低频混频器。本文使用0.18μmCMOS工艺中的V-NPN晶体管设计了一个双极型有源混频器。仿真结果显示,工作电压为3.3V,LO频率为50KHz,RF频率为40KHz时,该双极型有源混频器的电压增益为18.3dB,NFdsb为15.99dB,等效输出噪声,P1dB为-9.88dBm,IIP3为-1.65dBm。With the development of sonar communication technology, it is necessary to design the low noise low frequency mixer for low frequency receiver,using CMOS technology. Since the comer frequency of flicker noise for MOSFETs is usually about a few MHz, the mixer composed of MOSFETs has very high flicker noise and does not suit for low frequency receiver. This paper reports the characteristics of the parasitic vertical NPN （V -NPN）transistors, whose comer frequency of flicker noise is about a few KHz, in deep N -well CMOS technology ,and designs a novel double - balanced bipolar mixer wiht V - NPN transistors,which is suitable for low frequency receiver, the proposed mixer is designed using 0. 18μm CMOS technology. Simulation results show that,the proposed mixer has 18. 3dB of voltage conversion gain, 15. 99dB of NFd,b ,32. 4nV/μHz of equivalent output noise, -9. 88dBm of Pads, and - 1.65dBm of IIP3 when the supply voltage is 3.3V and the frequency of LO signal is 50KHz.

关 键 词：双极型有源混频器 CMOS工艺 垂直寄生NPN晶体管 

分 类 号：TN773[电子电信—电路与系统]