基于FPGA的DVB-ASI信号接收的实现  

Design of the DVB-ASI acquisition based on FPGA

作　　者：刘雄飞[1] 邓强华[1] 

机构地区：[1]中南大学物理科学与技术学院,湖南长沙410083

出　　处：《微计算机信息》2010年第11期127-129,共3页Control & Automation

摘　　要：DVB-ASI(Digtal Video Broadcasting-Asynchronous Serial Interface)信号是一种高速的异步串行信号,在对其接收时常会出现误码率过高,解码困难等情况。以往DVB-ASI信号的接收常采用专用的通信接收处理芯片,成本较高,本文采用芯片为altera公司的EP2C8Q208C8,其中采用多重相位技术和过采样实现了时钟的恢复,有效地降低了误码率。然后对采样的数据进行字对齐,8B/10B解码,字同步,经过包同步后输出符合MPEG-2标准的TS(Transport Stream)流。系统的所占资源为610个LE,占芯片总资源的7.4%,工作频率为135MHZ。DVB-ASI is a kind of asynchronous serial signal with high speed. When it is received, there are always some problems, such as, high bit error rate, difficult decoding, etc. As usual, DVB-ASI is received by special communication receiving treatment chips with high cost. However, this article adopts the chip EP2C8Q208C8 from ALTERA company. The chip adopts multiple phases technique and oversample, which can realize the recovery of the clock, and lower the bit error rate effectively.Then the sampled parellel datas are operated by word alignment , 8B/10B decoder, and word synchronization, packet synchronization and then output with transport stream consistented with the MPEG-2 standard. The logic resources in the system are 610 LE, and account for 7.4% of the total logic resources of the chip. Working frequency of the system is 135MHZ.

关 键 词：异步串行接口 8B/10B 时钟恢复 多重相位 过采样 

分 类 号：TN919.3[电子电信—通信与信息系统]