沟槽功率MOS器件的多晶Si填槽工艺研究  

Study on Poly Deposition Process for Power MOSFET Manufacture

作　　者：秦晓静 周建伟[1] 康效武[1] 

机构地区：[1]河北工业大学微电子技术与材料研究院,天津300401

出　　处：《半导体技术》2010年第4期365-368,共4页Semiconductor Technology

摘　　要：介绍了多晶Si薄膜的成膜机理及其在集成电路中的应用,针对沟槽功率MOSFET集成电路制造中两种主流多晶Si工艺的优点和不足进行了分析和对比。从栅氧化层厚度分布和Arriving Angle模型两个方面分析了沟槽中多晶Si空洞的形成机制。阐述了金属通过多晶Si空洞穿透Si衬底导致器件失效的理论,并通过失效器件的FIB分析对理论加以证实。最后基于Arriving Angle模型理论,在试验中改变沟槽顶端和底部宽度,将沟槽刻蚀成倒梯形的结构,以多晶Si填充沟槽经历高温退火工艺再进行SEM分析。分析结果证实,改变沟槽顶端和底部宽度可彻底消除沟槽中多晶Si的空洞,提高器件的可靠性。The mechanism of poly deposition and application of poly Si are introduced. The advantages and disadvantages of two major poly Si process for trench power MOSFET IC are compared. The theory of void formed during poly deposition or after high temperature anneal are discussed based on gate oxidation thickness distribution and Arriving Angle modle. The failure mechanism caused by metal digging into Si layer is described and it is verified by FIB for failed device. The width of trench from top to bottom position was adjusted based on the Arriving Angle model, deposited poly into trench, followed by a high temperature anneal process, and finally, the SEM profile of trench was obtained. The experiment results show that this method can prevent poly void and improve the reliability of device.

关 键 词：集成电路 沟槽 功率金属-氧化物-半导体场效应晶体管 多晶硅 晶粒 栅极 

分 类 号：TN305[电子电信—物理电子学]