一种基于差动放大器的超高速脉宽调整电路  

A High-Speed Pulse Width Control Circuit Based on Differential Amplifier

作　　者：朱璨[1,2] 徐鸣远[1,2] 沈晓峰[1,2] 冯雯雯[1] 

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060 [2]模拟集成电路国家级重点实验室,重庆400060

出　　处：《微电子学》2010年第2期270-273,282,共5页Microelectronics

摘　　要：设计了一种用于超高速A/D转换器的脉宽调整电路。以基准输出电压为参照,利用差动放大器输出控制时钟输出占空比,最高可工作在1.7 GHz时钟频率下,锁定精度为50%±1%;拥有20%～80%占空比输入,且能很好地抑制时钟抖动。电路采用0.18μm工艺制作,芯片面积为0.3 mm×0.1 mm,在1.9 V电源电压下,功耗小于40 mW。A high-speed pulse width control circuit was designed for high-speed A/D converter, in which differential dynamic amplifier output was used to control duty cycle of clock, with output voltage as reference. Operating at 1.7 GHz, this circuit can fast lock duty cycle at 50%±1%and work at 20%-80% of duty cycle input, and further more, it can also suppress clock jitter. Fabricated in 0. 18μm CMOS process, the device occupies a chip area of 0. 3 mm×0. 1 mm, and consumes less than 40 mW of power from a single 1.9 V supply.

关 键 词：差动放大器 脉宽调整电路 时钟稳定电路 

分 类 号：TN722.57[电子电信—电路与系统]