用于超宽带接收机的高速低复杂度模拟自动增益控制环路  

High-speed and low-complexity analog automatic gain control loop for UWB receiver

作　　者：刘萌萌[1] 张盛[2] 王硕[1] 张建良[1] 周润德[1] 

机构地区：[1]清华大学微电子学研究所,清华大学信息科学与技术国家实验室微电子学部,北京100084 [2]清华大学深圳研究生院,广东深圳518055

出　　处：《电路与系统学报》2010年第2期70-74,共5页Journal of Circuits and Systems

基　　金：973国家重点基础发展项目(2006CB302702);863国家重点科研项目(2007AA01Z2B3)

摘　　要：在射频接收机中,自动增益控制环路(AGC)根据接收信号幅度控制放大器增益,向后级模数转换器(ADC)提供恒定幅度的信号,以实现不同强度信号的正确接收。在超宽带(UWB)接收机中,极大的信号带宽给AGC的设计提出了挑战。本文提出了一个用于超宽带(UWB)接收机的模拟自动增益控制环路(AGC)。该AGC环路采用多级可变增益放大器(VGA)串联的放大器结构,通过峰值检测电路和模值运算电路检测输出复信号模值的峰值,和参考电位比较后反馈控制VGA的增益,从而得到恒定幅值的ADC的输入。整个电路结构简单,复杂度低。基于HJ0.18μmCMOS工艺的仿真结果表明,本文提出的AGC工作在500MHz带宽下,增益调节范围达40dB,三阶交调点为20dBm,能够满足UWB接收机的要求。AGC （Auto-Gain-Control） is used in RF receivers to adjust gain of amplifier and achieve fixed output signal amplitude, thus signals with different energy can be received correctly. UWB （Ultra-Wideband） signals, whose bandwidth is extremely wide, give AGC design a new challenge. The paper presents a high-speed low-complexity circuit structure of analog AGC loop for UWB receiver. The AGC loop takes advantage of multi-stage variable gain amplifiers （VGA） for controllable and high gain, while using peak-detector and absolute-value-calculator to achieve the maximum absolute-value of complex signal. Comparing the maximum absolute-value to the reference voltage, the circuit creates a feed-back gain control voltage which can control gain of VGA to make power level of the output in accordance with the regulated input signal amplitude of ADC. Based on HJ 0.18~m CMOS technology, simulation results show that the proposed AGC loop can achieve a 40dB gain control while 3dB bandwidth is more than 500MHz, and IP3 is 20dBm, which proves that the AGC presented can meet the requirement of UWB receiver.

关 键 词：AGC UWB VGA 低复杂度 

分 类 号：TN432[电子电信—微电子学与固体电子学]