基于Xilinx SoPC的可重构嵌入式计算系统的研究与设计  

Study and Design of Reconfigurable Embedded Computing System Based on Xilinx SoPC

作　　者：张宇[1] 冯丹[1] 

机构地区：[1]华中科技大学计算机科学与技术学院,武汉430074

出　　处：《计算机科学》2010年第5期274-277,281,共5页Computer Science

基　　金：973国家基础研究项目(No.2004CB318201)资助

摘　　要：由于应用种类、实时性以及处理效率等要求,高性能嵌入式计算硬件平台需要具备相当的计算能力以及一定的适应性。为此提出了一种基于Xilinx FPGA的动态可重构的片上系统设计方案。系统采用专用硬件来执行计算密集型任务,运用动态可重构技术来支持硬件处理模块功能的动态配置。研究了Xilinx可编程片上系统上的3种硬件加速方案:CPU协处理器、PLB扩展加速器和MPMC扩展加速器。实验数据表明MPMC加速器性能最优。在Vir-tex5 FPGA器件上实现了可动态重构的MPMC加速器,以128位AES加密、解密两个功能模块为例,从硬件资源占用率、重构延时等角度考察了可重构系统的特点。The high performance embedded computing systems need considerable computational power and flexibility to meet various application rectuirements. A reconfigurable SoPC design based on Xilinx FPGA was presented. The system uses a dedicated hardware accelerator to process computational intensive tasks, and the accelerator can be dynamically configured during run-time. The hardware processing engine can be coupled to the host system as a CPU coprocessor,a PLB accelerator or an MPMC accelerator. Based on the experimental result that the MPMC accelerator had the highest performance, a reconfigurable MPMC accelerator was designed and integrated into the SoPC system. I}he experiments used 128-bit AES encryption and decryption as case studies. Features such as hardware resource utilization and reconfi guration latency for the reconfigurable system were also studied.

关 键 词：嵌入式计算 可编程片上系统 可重构计算 协处理 加速器 

分 类 号：TP36[自动化与计算机技术—计算机系统结构]