基于Verilog HDL的UART模块设计与仿真  

Design and simulation of UART module based on Verilog HDL

作　　者：魏巍[1] 赵红东[1] 

机构地区：[1]河北工业大学信息工程学院,天津300401

出　　处：《电子设计工程》2010年第5期155-157,共3页Electronic Design Engineering

摘　　要：通用异步收发器UART常用于微机和外设之间的数据交换,针对UART的特点,提出了一种基于Verilog HDL的UART设计方法。采用自顶向下的设计路线,结合状态机的描述形式,使用硬件描述语言设计UART的顶层模块及各个子模块,从而使整个设计更加紧凑、可靠。同时采用参数化的设计方法,增强系统的可移植性。仿真结果表明,该系统可支持标准异步串行传输RS-232协议,可集成到FPGA芯片中使用。UART （Universal Asynchronous Receiver Transmitter）is applied to data exchange between the microcomputer and peripherals,according to the characteristics of the UART,this paper puts forward an UART design method based on Verilog HDL. Top-down design process is researched,uses the description form of FSM,Verilog HDL is used to design the salve module and the top module of UART,so it can make whole design tighter and more reliable. The system compatibility is enhancing due to the parametric design method. The simulate results indicate that the UART design can be used in situations such as transmission using standard asynchronous serial RS-232 protocol and integrate into the FPGA chip to use.

关 键 词：VERILOG HDL 通用异步收发器(UART) 状态机 仿真 

分 类 号：TN47[电子电信—微电子学与固体电子学]