现代层次化可编程逻辑器件软件系统FDE2009  

FDE2009 Software System for Programmable Logic Device with Hierarchical Architecture

作　　者：谢丁[1] 邵赟[1] 来金梅[1] 王健[1] 陈利光[1] 王元[1] 俞建德[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《电子学报》2010年第5期1136-1140,共5页Acta Electronica Sinica

基　　金：国家自然科学基金(No.60876015);国家863高技术研究发展计划(No.2007AA01Z285)

摘　　要：本文提出并实现了适用于现代层次化结构的FPGA芯片的CAD软件系统:FDE2009(FPGA Development Environment).该软件系统不但由工艺映射,布局布线,位流生成,编程下载等功能模块构成了一套完整的FPGA CAD流程,并且根据现代FPGA芯片层次化的结构特点,提出了逻辑分层的布局思想及由底至上逐层构建布线资源图的算法,提高了硬件资源的利用率及程序的运行效率.此外,本软件自定义了一套使用扩展性标志语言的文件系统,从而使其具有一定的通用性及良好的扩展性.软硬件协同测试结果表明该软件系统各模块功能正确,并能配合硬件高效的实现各类功能电路,是一套实用的FPGA软件系统.A CAD software system named FDE2009 （FPGA Development Environment） is introduced to be applied to modem hierarchical FPGAs. This system consists of a complete CAD flow of software modules including technology mapping, placemere,muting,bit file generator and programming. According to the feature of hierarchical modem FPGAs, we＇ ve introduced the idea of logical layer in placement and a bottom-up way to build muting resource graph,in order to enhance the utilization efficiency of logical resources and reduce the runtime of our system. A documentary system with extendable tags is also defined and integrated in FDE2009, which allows the system to digest information for further development. Co-operational testing of both software and hardware system shows the correctness, efficiency, and practicality of FDE2009, and gives a stable result of the co-operation between FDP2009 software system and the corresponding FPGA chips.

关 键 词：现场可编程门阵列 FDE2009软件系统 工艺映射 布局 布线 

分 类 号：TN47[电子电信—微电子学与固体电子学]