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机构地区:[1]浙江大学信息科学与电子工程学系,浙江杭州310027
出 处:《浙江大学学报(工学版)》2010年第4期625-631,共7页Journal of Zhejiang University:Engineering Science
基 金:国家"863"高技术研究发展计划资助项目(2006AA01Z273)
摘 要:通过对典型载波同步环路的分析与比较,提出一种新型的适用于TCM-8PSK短包高速跳频接收机的快速载波同步环路.对2种鉴相器(基于逐幸存处理(PSP)的鉴相器、锯齿形鉴相器)与2种环路滤波器(一阶环、二阶三型环)分别组合得到的4种环路结构的误比特率(BER)进行仿真,结果表明在短包传输方式以及AWGN信道条件下,基于PSP的鉴相器结合一阶滤波器的环路结构具有最佳BER性能.利用Monte Carlo算法得到该环路的相位误差统计信息,并对原鉴相器的鉴相特性曲线进行改进,减小了由相位误差产生的环路噪声.改进后的鉴相器结合一阶滤波器的新载波同步环路便于硬件实现,在最大载波频偏为1‰倍符号率以及中频信号通过信噪比为5~15dB的AWGN信道条件下,BER较理论值损失0.4~1.5dB,而较原环路提升0.5~1.5dB.该仿真结果与硬件实际测量结果一致.A new scheme of digital phase-locked loop (DPLL) based demodulator was presented for the fast carrier synchronization required in TCM-8PSK short-packet fast-frequency-hopping system.A comparison of bit error rate (BER) simulation was made amongst 4 DPLL-based TCM-8PSK demodulators,that is per-survivor processing (PSP) based phase detector and saw-tooth phase detector combined with first-order and second-order loop filters,respectively.Results showed that the DPLL comprising PSP-based phase detector and first-order loop filter exhibited outstanding BER performance through an AWGN channel and under short-packet constraints.Statistical information regarding the phase error acquired from this DPLL was obtained by Monte Carlo method,and improvements were made to the S-curve of the original phase detector,which reduced both the loop noise caused by phase error acquisition and the hardware overhead for implementation.BER simulation of the new DPLL adopting improved phase detector and first-order loop filter showed a 0.4 — 1.5 dB loss towards the theoretical values but also a 0.5 — 1.5 dB gain towards the original DPLL,when the IF signals were transmitted through an AWGN channel with SNR ranging from 5 to 15 dB and the carrier frequency offset was set up to 1‰ baud rate.This simulation result was in accordance with the practical performance of the implementation.
关 键 词:TCM-8PSK 高速跳频系统 载波同步 数字锁相环 逐幸存处理
分 类 号:TN911.8[电子电信—通信与信息系统]
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