一种应用于10位逐次逼近ADC的比较器设计  

The Design of Comparator for Successive Approximation ADC

作　　者：肖培磊[1] 胡小琴[1] 李竞春[1] 

机构地区：[1]电子科技大学,成都610054

出　　处：《电子与封装》2010年第5期17-21,共5页Electronics & Packaging

摘　　要：文中提出了一种应用于10位逐次逼近ADC的比较器。该比较器包括预放大器、中间放大器、输出驱动级及共模电平缓冲器。整体开环设计,采用多级级联的形式以满足增益和速度的要求;采用输出失调消除技术进行失调校正;为了提高共模电平的驱动能力和缩短建立时间,采用分压电路加单位增益放大器的结构。基于3.3V电源电压、TSMC0.18μmCMOS工艺下,仿真结果表明,完全满足最高采样频率30MHz、10位精度的模数转换器要求。A novel self calibrating input offset voltage CMOS comparator is assigned. The comparator includes three preamplifiers, a V buffer and offset cancelling circuits. The overall open-loop design, in the form of multilevel cascading to meet the gain and speed requirements; use of technology to eliminate the output offset correction; to enhance the common mode level of the drive capability and shorten the setup time, using sub- unity gain piezoelectric Luke amplifier structure. Based on 3.3V power supply and TSMC 0.18u m CMOS process, the simulated result shows that it meets the requirement ofa 30MHz, 10 resolution successive approxi- mationADC.

关 键 词：比较器 缓冲器 失调校正 放大器 

分 类 号：TN402[电子电信—微电子学与固体电子学]