一种高效功耗攻击物理实验平台研究  

Research of an Efficient Power Analysis Physical Experiment Platform

作　　者：李浪[1,2] 李静[2] 李仁发[2] 吴克寿[3] 

机构地区：[1]衡阳师范学院计算机系,衡阳421008 [2]湖南大学计算机与通信学院,长沙410082 [3]厦门理工学院计算机系,厦门361024

出　　处：《计算机科学》2010年第6期75-77,共3页Computer Science

基　　金：国家自然科学基金(60903203);湖南省科技计划项目(2009GK3023)资助

摘　　要：功耗攻击是近年来一种对加密芯片密钥攻击最大的威胁,加密芯片功耗攻击与防御成为了研究热点。但功耗分析的实验平台构建却比较困难。以AES加密算法芯片为例,构建了一个基于FPGA的高效功耗攻击物理实验平台。详细叙述了物理实验平台的建立过程、实验结果。该功耗攻击物理实验平台构建相对简单,实验运算速度较快,且具有加密算法易于修正的灵活性,可以方便地对加密算法的功耗特性进行改进与验证。在功耗分析模型上,设计了一种高效功耗攻击模型,该模型在差分统计速度上提高了一个数量级,可为抗功耗攻击研究进行快速实验提供参考。Power analysis attack has become a great threat to encryption chips. Attacks and defense of power analysis have become the research hotspot. However, experimental platform of power analysis is more difficult to build for researchers. AES encryption algorithm was used to build a high-performance FPGA-based physical experiment platform for power analysis as an example. The process of establishing the physical experimental platform was described in detail. The platform is relatively simple, fast test speed, flexibility. It will be convenient to verified for the encryption algorithm of the power. The efficient power analysis model was proposed. It can improve the exprimental speed in the differential statistics.

关 键 词：功耗分析 AES 物理实验平台 功耗模型 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]