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机构地区:[1]兰州大学静电感应器件研究所 [2]北京航空航天大学材料理化研究中心
出 处:《半导体技术》1999年第1期36-38,共3页Semiconductor Technology
摘 要:对静电感应器件的栅源击穿特性做了实验研究。结果表明:当使用高阻单晶材料(ND=1×1014cm-3)作为芯片的衬底和沟道,沟道的半宽度小于零栅压耗尽层宽度且源区外延层掺杂浓度较高(Nepi>1×1016cm-3)时,器件的击穿电压BVgs0基本上局限在10V以下,与外延层的厚度没有明显关系。作者指出,静电感应器件栅源击穿的特点是由于沟道宽度较窄和源区与沟道区掺杂浓度差异较大两方面的因素共同决定的。在这种情况下,栅源击穿电压BVgs0与半导体的击穿电场Eb和沟道宽度W的关系可表示为BVgs0=1/2EbW。提高BVgd0的有效途径应是尽可能地使外延层的掺杂浓度和沟道(衬底)的掺杂浓度相接近。The gate source breakdown performance of static induction transistor was studied experimentally.Using much higher doped source epitaxial layer( N epi >1×10 16 cm -3 )than the single crystal silicon substrates( N D=1×10 14 cm -3 ),it has been found that the gate source breakdown voltage BV gs0 as a function of the channel width was li mited lower than 10V,as long as the channel width was designed smaller than the depletion layer width of gate channel junction at zero gate bias,which is necessary for good operation of static induction devices.Under these conditions,the BV gs0 had no obvious relation to the epi layer thickness.It was pointed out that such breakdown behaviors were due to two major factors: smaller channel width; and larger difference between N epi and N D,and that BV gs0 could be estimated as a function of the breakdown field strength E b and the channel width W : BV gs0 =1/2 E b W .It was also shown that,making the dopant of source epi layer as equal as possible to that of the substrate could be a practical measure to improve the gate source breakdown of static induction devices.
分 类 号:TN303[电子电信—物理电子学]
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