针对Xilinx可编程片上系统的硬件加速方案的研究  

Study of Hardware Accelerating Schemes for Xilinx System on Programmable Chip

作　　者：张宇[1] 冯丹[1] 

机构地区：[1]华中科技大学计算机科学与技术学院,湖北武汉430074

出　　处：《小型微型计算机系统》2010年第6期1147-1151,共5页Journal of Chinese Computer Systems

基　　金：国家"九七三"重点基础研究项目(2004CB318201)资助

摘　　要：当前嵌入式计算应用不断增加,嵌入式系统需要具备相当的处理能力以满足应用需求.在系统中耦合一个专用硬件处理模块来加速某种计算机密集型应用是一种被广泛采纳的有效手段.针对基于Xilinx FPGA的可编程片上系统,从体系结构角度分别研究了三种形式的硬件加速方案:(1)与CPU耦合的协处理器;(2)挂接在PLB总线上的加速器;(3)挂接在MPMCSwitch Fabric上的加速器.分析了三种方案各自的特点.在实验环节选取了128位AES加密算法,并在Xilinx Virtex5器件上做了硬件实现,结果表明基于MPMC扩展的加速器方案性能较好,CPU占用率最低.With the trend of increasing popularity on embedded computing applications,embedded systems need to embrace considerable computing power to meet the requirements of the applications.A widely adopted method to improve the performance is to integrate dedicated hardware processing engines.Targeting the Xilinx System-on-Programmable-Chip,we studied three methods for hardware acceleration：（1）CPU coprocessor;（2）hardware accelerator that placed on PLB bus;（3）hardware accelerator connected with MPMC.We analyzed each method and conducted experiments using 128-bit AES encryption as a case study.The experimental results show that we can get the best performance and lowest CPU utilization using the MPMC hardware accelerator.

关 键 词：嵌入式计算 可编程片上系统 协处理 加速器 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]