建立高速数字I/O缓冲器宏模型的模糊逻辑方法  

Macromodeling of high-speed digital I/O buffers by means of fuzzy logic

作　　者：沈建国[1] 郭裕顺[1] 刘公致[1] 

机构地区：[1]杭州电子科技大学,浙江杭州310018

出　　处：《电路与系统学报》2010年第3期48-53,共6页Journal of Circuits and Systems

基　　金：国家自然科学基金资助项目(60672013)

摘　　要：如何构造精确有效的数字电路I/O缓冲器宏模型用于系统级的仿真,是高速电路信号完整性分析中的重要问题。本文提出了一种基于模糊逻辑,对数字电路的I/O缓冲器瞬态行为建模的方法。采用一阶Sugeno模糊系统,用平均分割法生成初始模型,再通过BP-最小二乘混合学习算法消除误差。模型可综合成SPICE环境下的子电路,应用十分方便。计算实例表明方法是有效的。The macromodeling of the digital I/O buffers is one of the key issues in the evaluation of the signal integrity for high-speed circuits at the board or system level. A new method for the behavior macromodeling of the digital I/O buffers by means of fuzzy logic is proposed in this paper. The first order Sugeno fuzzy system is employed in the modeling. The model is initially constructed using grid partition and then trained by the hybrid BP-least square solution algorithm. The finally obtained model can be implemented as a SPICE subcireuit. Its accuracy and efficiency is verified by the numerical simulation of several actual digital circuits.

关 键 词：高速数字I/O缓冲器 电路宏模型 信号完整性分析 模糊逻辑 

分 类 号：TN334[电子电信—物理电子学]