一种用于高速高精度A/D转换器的时钟稳定电路  

Clock Stabilizer for High Speed and High Resolution Pipeline A/D Converter

作　　者：徐鸣远[1,2] 沈晓峰[1,2] 朱璨[1,2] 

机构地区：[1]中国电子科技集团公司第二十四研究所,重庆400060 [2]模拟集成电路国家级重点实验室,重庆400060

出　　处：《微电子学》2010年第3期309-312,316,共5页Microelectronics

摘　　要：设计了一种完全满足高速高精度流水线A/D转换器的时钟稳定电路。通过在延迟环路中加入启动电路,使环路能在小于300 ns内快速锁定占空比,锁定精度为50%±1%。拥有20%-80%的占空比输入,且能很好地抑制外部时钟抖动,时钟抖动小于100 fs。电路采用0.35μm工艺制作,芯片面积为0.5 mm×0.3 mm,在3.3 V电源电压下,功耗小于78 mW。A clock duty cycle stabilizer was designed for high speed and high resolution pipeline A/D converter.By introducig a start-up circuit into delay loop,the loop circuit could lock duty cycle rapidly with an accuracy of 50%±1% in 300 ns.This circuit had 20%-80% of duty cycle input,and clock jitter could be suppressed to less than 100 fs.Implemented in 0.35 μm CMOS process,the circuit occupies a chip area of 0.5 mm × 0.3 mm and dissipates less than 78 mW of power from 3.3 V supply voltage.

关 键 词：A/D转换器 电荷泵 时钟稳定电路 

分 类 号：TN45[电子电信—微电子学与固体电子学]