基于FPGA非相干包络码跟踪环设计  

Non-Coherent Enveloped Code DLL Design based on FPGA

作　　者：裴军[1] 胡正群[1] 胡超[1] 

机构地区：[1]中国科学院国家天文台,北京100012

出　　处：《通信技术》2010年第5期50-52,55,共4页Communications Technology

基　　金：国家重点基础研究发展计划(973)资助项目(批准号:2007CB815500)

摘　　要：非相干的包络同步码跟踪环不依赖载波跟踪的相位特性,可以解决在信噪比非常低的条件下的本地扩频码和接收扩频码的码同步,进而完成扩频码的稳定跟踪。根据非相干的包络码跟踪环的原理,利用Verilog设计了一个完整的非相干的包络码跟踪环的电路。在设计过程中利用IP核中的乘法器、IIR滤波器、DDS数字频率合成器,简化设计难度并快速形成设计模块。在采用XilinxISE实现上述关键部分电路的设计基础上,同时利用SynplifyPro对设计模块进行了综合,并在Modelsim6.0中对电路进行了功能波形仿真,证明了设计的可行与合理性。这种解决方案相对常规方法既具有软件验证的灵活性,又具有硬件的执行效率。Non-coherent enveloped spreading code DLL relies on no phase characteristics of carrier and could be used to solve exact code in-phase between the local spreading code and receiving relative spreading code under a very low C/N 0,and according to its code tracking principle,the design of functional modules are completed with Verilog HDL.During the design process,the use of various available IP cores,such as multipliers,IIR filters,DDS modules,could simplify the design complexity and form rapidly the design modules.Based on the implementation of critical circuit design,the functional modules are verified and simulated with wave bench by SynplifyPro and Modelsim 6.0 tools,and the feasibility and reliability of the design is also proved.This proposed design is more flexible in software verification and executable in hardware assembles than the conventional design.

关 键 词：FPGA 码跟踪环 VERILOG HDL 

分 类 号：TN962[电子电信—信号与信息处理]