IEEE802.16e标准LDPC译码器设计与实现  

Design and Implementation of 802.16e Standard LDPC Decoder

作　　者：杨建平[1] 陈庆春[1] 

机构地区：[1]西南交通大学信息科学与技术学院,四川成都610031

出　　处：《通信技术》2010年第5期84-86,206,共4页Communications Technology

基　　金：教育部科学技术研究重点计划项目(NO.107096);西南交通大学校科研基金项目资助

摘　　要：LDPC码自在上个世纪90年代被重新发现以来,以其接近香农极限的差错控制性能,以及译码复杂度低、吞吐率高的优点引起了人们的关注,成为继Turbo码之后信道编码界的又一研究热点。利用FPGA设计并实现了一种基于IEEE802.16e标准的LDPC码译码器。该译码器采用偏移最小和(Offset Min-Sum)算法,其偏移因子β取值为0.125,具有接近置信传播(Belief Propagation)算法浮点的性能。译码器在结构上采用了部分并行结构,可以灵活支持标准中定义的所有码率和码长的LDPC码的译码。此外,该译码器还支持对连续输入的数据块进行处理,并具有动态停止迭代功能。硬件综合结果表明,该译码器工作频率为150MHz时,固定15次迭代,最低可达到95Mb/s的译码吞吐率,完全满足802.16e标准的要求。Since its re-discovery in 1990s,LDPC codes have attracted much attention and become an another focus in channel coding filed after Turbo codes because of their error correction capability close to Shannon limit,and low decoding complexity and high decoding throughput.In this paper,a LDPC decoder based on the IEEE802.16e standard is designed and implemented with FPGA.Offset Min-Sum algorithm is employed,which with the offset factor β=0.125,is close to the floating point performance of Belief Propagation algorithm.With the partly paralleled architecture,the decoder could flexibly support all kinds of code rate and code length defined in the standard.Moreover,this decoder could also support the early iteration stopping criterion and the on-the-fly change of code rate and code length.Hardware synthesis results show that the decoder supports a throughput up to more than 95 Mb/s by fixed 15 iterations at the clock frequency of 150MHz,and thus meets the requirements of the IEEE802.16e standard.

关 键 词：IEEE802.16E LDPC码译码器 偏移最小和算法 FPGA 

分 类 号：TN764[电子电信—电路与系统]