读写通道基于τ因子内插时钟恢复模型设计与实现  

Design and Implementation of a Servo Interpolated Timing Recovery Model in the Read/Write Channel Based on the τ Factor

作　　者：丁红[1] 王庆东[2] 

机构地区：[1]上海第二工业大学计算机与信息学院,上海201209 [2]华中科技大学计算机科学与技术学院教育部外存储国家专业实验室,湖北武汉430074

出　　处：《计算机工程与科学》2010年第7期76-79,共4页Computer Engineering & Science

基　　金：国家自然科学基金资助项目(60303031);上海市教育高地建设资助项目

摘　　要：读写通道是介于磁盘读写头与设备控制器之间的电子电路,实现数据写入和可靠的恢复。伺服信号采样时钟是伺服信号检测的重要组成部分,其设计的目标是在提高伺服信号传输速率的同时维持低的误码率,这就对通道的数据采样处理以及时钟恢复电路的设计提出了严格的要求。本文通过对读写通道伺服的分析,对常用的由锁相环构成的伺服时钟恢复电路进行改进,在线性插值时钟恢复的基础上提出了基于τ因子内插时钟恢复模型,并推导出τ因子插值滤波器系数算法,还给出了伺服时钟恢复的硬件及FPGA的设计与实现方案,最后给出了基于线性插值和基于τ因子内插时钟恢复试验。测试结果证明,采用基于τ因子内插滤波器模型可以获得更好的谐波频谱。The read/write channel is the electronic circuit between the readwrite head for disks and the device controller,and its main function is to write and recover data reliably.The servo signal sampling clock is an important part of servo signal detection and its design goal is to improve the servo signal transmission rate as well as maintain the low BER,which makes strict demands on data sampling processing and clock recovery circuit design.This paper offers the servo interpolated timing recovery model based on the τ factor after analysizing the current PLL timing recovery implementation,and adopts a better solution.This paper also deduces the coefficient of interpolator,then studies the realization of the interpolator by hardware and FPGA.Through a comparison test with the linear interpolation scheme,the interpolated model can obtain better harmonic frequency.

关 键 词：读写通道 伺服信号 &tau 因子 内插时钟恢复模型 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]