一种基于FPGA的低功耗、容错状态机设计方法  

A FPGA-based Design Method of Low Power Fault-tolerance Finite State Machine

作　　者：李列文[1,2] 桂卫华[1] 胡小龙[1] 

机构地区：[1]中南大学信息科学与工程学院,湖南长沙410075 [2]长沙师范学校电子信息工程系,湖南长沙410100

出　　处：《湖南大学学报（自然科学版）》2010年第6期77-82,共6页Journal of Hunan University:Natural Sciences

基　　金：国家自然科学基金重点资助项目(60634020)

摘　　要：针对FPGA(Field Programmable Gate Array)在航空航天领域应用面临的可靠性和功耗问题,提出了一种适于FPGA实现的低功耗、容错有限状态机设计方法.该方法与传统FPGA中实现状态机占用布线资源、查找表、寄存器等资源的思想不同,它将状态机映射到FPGA内嵌块RAM,同时采用两块RAM构成双模冗余结构,通过比较两块RAM输出数据的一致性确定RAM中数据出错的情况,并结合奇偶校验进行检错与纠错.实验结果表明:与经典的三模冗余方法相比,该方法有更低的功耗和更高的可靠性,并能对一位错误实现在线纠错.Considering the reliability and power consumption problems of（Field Programmable Gate Array）FPGA in aviation and spaceflight application,a new design method of low power and fault-tolerance finite state machine suitable for FPGA has been proposed.Different from traditional occupying routing resources,looking up tables and registers,this method was realized by mapping finite-state machines into the embedded blocks RAM of FPGA and employing two RAM blocks to compose the duple-redundancy structure to confirm data errors in RAM by comparing the consistency of the two blocks RAM output data and combining the parity check for error detection and correction.The experiment results have shown that this method has the advantages of lower power and higher reliability,and can achieve an error on-line error correction,compared with traditional triple-redundancy methods.

关 键 词：低功耗 有限状态机 容错 现场可编程门阵列 

分 类 号：TP368[自动化与计算机技术—计算机系统结构] TN873[自动化与计算机技术—计算机科学与技术]