适用于IEEE 802.11n的高速低功耗Viterbi译码器的设计  

A High-Speed and Low-Power Viterbi Decoder Design for IEEE 802.11n Applications

作　　者：朱勇旭[1] 吴斌[1] 周玉梅[1] 张振东[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2010年第7期10-14,共5页Microelectronics & Computer

摘　　要：针对IEEE 802.11nSOC对信道编码的多码率、高吞吐率的要求,设计了适用于IEEE 802.11n卷积码的Viterbi译码器,具有高吞吐率,低功耗特点,可支持1/2,2/3,3/4,5/6码率.译码器采用全并行的加比选(ACS)单元,最高位清零防溢出处理,采用了一种可降低功耗的寄存器交换法,可有效减少寄存器翻转动态功耗.采用SMIC0.13μm CMOS工艺设计并实现了该译码器,时钟频率为240MHz时,最大数据吞吐率为480Mb/s,功耗为25mW.The IEEE 802.11n SOC requests high throughput and multi-rate encoder and decoder in channel coding. In this paper,a Viterbi decoder with high throughput and low power is presented for convolutional codes in IEEE 802.11n standard,capable for 1/2,2/3,3/4,5/6 rates. This decoder fulfills full-parallel ACS units,MSB over-floating protection,and a registers exchange scheme for low power design is used to cut off the dynamic power in register effectively. The decoder has been implemented by SMIC 0.13-μm CMOS process,and the max throughput is 480Mb/s with the power of 25mW at 240MHz frequency.

关 键 词：VITERBI译码器 MIMO-OFDM WLAN 高吞吐率 低功耗 ASIC 

分 类 号：TN403[电子电信—微电子学与固体电子学]