Sigma Delta调制器高效行为级建模  

Efficient Behavioral Modeling of Sigma Delta Modulator

作　　者：许金波[1] 陈晓飞[1] 刘占领[1] 林双喜[2] 李思臻[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074 [2]武汉工程大学电气信息学院,湖北武汉430073

出　　处：《微电子学与计算机》2010年第7期69-73,共5页Microelectronics & Computer

基　　金：中国博士后科学基金项目(20080440933)

摘　　要：提出一种宏模型和Verilog-A模型相结合的方法对两阶、1位量化的Sigma Delta调制器进行建模.对调制器中的关键模块采用宏模型建模,对功能性模块采用Verilog-A描述.在Cadence环境下,基于华虹NEC0.25μm CMOS工艺对模块进行设计和仿真,并与实际电路模块仿真结果和仿真时间进行对比,给出两种情况下调制器总体电路的SNR仿真结果.结果显示:这种建模方法既达到了较高的精度,又取得了较快的仿真速度.Behavioral modeling of the second-order,one-bit quantizer modulator using a method of macro-model combined with Verilog-A model is presented. The key modules of the modulator are modeled in macro-model and the functional modules are described in Verilog-A. The modules are designed and simulated in the Cadence environment based on Huahong NEC 0.25μm CMOS process. The results and time of the simulation of the modules＇ are compared with the circuit＇s,and the SNR of the overall circuit of the modulator in both conditions are presented. The results show that this method of modeling could achieve a higher accuracy and faster simulation speed.

关 键 词：宏模型 VERILOG-A SIGMA Delta调制器 行为级 建模 

分 类 号：TN4[电子电信—微电子学与固体电子学]