LTE标准下Turbo码编译码器的集成设计  

The integrated design of Turbo encoder and decoder in LTE

作　　者：朱铁林[1] 赵仲元[2] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001 [2]哈尔滨工业大学电子与信息工程学院,黑龙江哈尔滨150001

出　　处：《电子技术应用》2010年第7期31-34,共4页Application of Electronic Technique

摘　　要：针对固定码长Turbo码适应性差的缺点,以LTE为应用背景,提出了一种帧长可配置的Turbo编译码器的FPGA实现方案。该设计可以依据具体的信道环境和速率要求调节信息帧长,平衡译码性能和系统时延。方案采用"自顶向下"的设计思想和"自底而上"的实现方法,对Turbo编译码系统模块化设计后优化统一,经时序仿真验证后下载配置到Altera公司Stratix III系列的EP3SL150F1152C2N中。测试结果表明,系统运行稳健可靠,并具有良好的移植性;集成化一体设计,为LTE标准下Turbo码ASIC的开发提供了参考。For the poor adaptability of fixed frame length Turbo codes, an FPGA implementation of Turbo encoder and decoder whose frame length can be configured is proposed in LTE. The design is able to adjust its interleaving depth according to the channel environment and the request of data rate, so that the decoding performance and system delay achieve the best balance. The ＂top-down＂ design thinking and the ＂bottom-up＂ implementation method is adopted. The Turbo encoder and decoder are optimal unified after modular design. By means of timing simulation, the design is configured to EP3SLISOFl152C2N of Ahera＇s Stratix Ⅲ family. Test results show that the system is running stable and reliable, and has good portability. The integrated design provides a reference for developing ASIC of Turbo codes in LTE.

关 键 词：TURBO码 FPGA LTE 

分 类 号：TN764[电子电信—电路与系统]