10bit 40MS/s流水线模数转换器的研制  

Research and Development of 10 bit 40 MS/s Pipelined A/D Converters

作　　者：陈利杰[1,2] 周玉梅[1] 卫宝跃[1] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]内蒙古科技大学科技中心,内蒙古包头014010

出　　处：《半导体技术》2010年第7期727-731,共5页Semiconductor Technology

基　　金：国家自然科学基金资助项目(60676015)

摘　　要：设计了一种10 bit 40 MS/s流水线模数转换器。通过采用自举开关和增益提升的套筒式共源共栅运放,保证了采样保持电路和级电路的性能。该模数转换器采用TSMC0.35μmCMOS3.3 V工艺流片验证,芯片核心面积为5.6 mm2。测试结果表明,该模数转换器在采样率为40 MHz输入频率为280 kHz时,获得54.5 dB的信噪比和60.2 dB的动态范围;在采样率为46 MHz输入频率为12.6 MHz时,获得52.1 dB的信噪比和60.6 dB的动态范围。A 10 bit 40 MS/s pipelined A/ D converters was designed.The gain-boosting amp and bootstrap switch were used to guarantee the performance of the sample and hold circuit（S/H） and the sub-stages.The ADC was fabricated in a 0.35 μm CMOS process and operates under a 3.3 V voltage,occupying 5.6 mm2.The measured results indicate that the ADC exhibits SNDR 54.5 dB,SFDR 60.2 dB for 280 kHz input frequency at 40 MS/s;and SNDR 52.1 dB,SFDR 60.6 dB for 12.6 MHz input frequency at 40 MS/s.

关 键 词：流水线模数转换 采样保持电路 运算放大器 自举开关 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]