片上异构多核DSP同步与通信的实现  

Implementations of Synchronization and Communication in Heterogeneous Multi-Core DSP

作　　者：刘建[1] 陈杰[1] 敖天勇[1,2] 许汉荆[1] 

机构地区：[1]中国科学院微电子研究所,北京朝阳区100029 [2]河南大学物理与电子学院,河南开封475001

出　　处：《电子科技大学学报》2010年第4期528-531,536,共5页Journal of University of Electronic Science and Technology of China

基　　金：国家863计划重点项目(2009AA011700)

摘　　要：设计了一个硬件信号量模块,可实现互斥和栅障等同步功能。与使用处理器原子操作指令相比,该方法具有指令数目少、执行效率高的优点。为提高存储器使用效率,基于便笺式存储器的结构特点,设计了具有绝对地址映射和虚拟地址映射两种寻址模式的共享程序存储器以支持指令存储空间复用。FPGA实验结果证明,该设计与传统的采用L2缓存方式相比,可以将多核处理器系统的程序性能提高14.7%。A hardware semaphore module is designed to support the synchronization primitives, such as mutex and barrier. Compared with the atomic instruction realization, the method executes efficiently and uses fewer instructions. Based on the structure of scratch-pad memory, a shared program memory with two addressing mode of absolute address mapping and virtual address mapping is designed to implement instruction space sharing, resulting in higher utility of memory. The result of FPGA simulation demonstrates that, the performance of the proposed design can achieve speed-up 14.7% compared with traditional shared L2 caches.

关 键 词：数字信号处理器 硬件信号量 共享存储 同步 

分 类 号：TN914.42[电子电信—通信与信息系统]