基于Cadence的DDRⅡ仿真设计  

DDRⅡ Simulation Design Based on Cadence

作　　者：赵海舜[1] 王志平[1] 季晓燕[1] 

机构地区：[1]中国电子科技集团公司第54研究所通信系统与网络专业部,河北石家庄050081

出　　处：《电子科技》2010年第8期5-8,14,共5页Electronic Science and Technology

摘　　要：针对DDRⅡ设计中高速信号的完整性和时序匹配问题,使用EDA工具Cadence仿真设计了DDRⅡ存储器的印制板。通过Cadence软件建立DDRⅡ信号拓扑结构、仿真信号的串扰、码间干扰、过冲等与信号质量相关的参数,从仿真波形中可以测量出与信号时序相关的参数,从而计算出信号的时序裕量,并为DDRⅡ信号设置约束进行布线。布线完成后,使用Cadence软件进行板后仿真,验证DDRⅡ信号的完整性和时序关系。并根据仿真结果,总结出部分设计规则。Aiming at the problem of high-speed signal integrity and timing mach in the DDRⅡ design,this paper presents the simulation design of PCB which includes DDRⅡ memory through the use of Cadence software.Cadence software is adopted to make topology of DDRⅡ signals and to get the parameters related to signal integrity,such as crosstalk,ISI,overshoot and so on.The parameters related to timing sequence of DDRⅡ signals can be obtained from the simulation waveform,and thereby the timing budget for DDRⅡ signals can be calculated to make constraints for them for the layout.After the layout,the post-route simulation is done in order to identify the signal integrity and timing sequence of the DDRⅡ signals.Some design guidelines are summarized based on the simulation results.

关 键 词：拓扑 仿真 信号完整性 信号质量 时序 

分 类 号：TN911.72[电子电信—通信与信息系统]