一种基于多数决定门的新型全加器的设计  

Design of a Novel Full Adder Based on Majority Gate

作　　者：方赟[1] 蔡艳慧[1] 钟传杰[1] 

机构地区：[1]江南大学信息工程学院,江苏无锡214122

出　　处：《微电子学》2010年第4期561-565,共5页Microelectronics

基　　金：科技部技术创新基金资助项目(07C262223201317)

摘　　要：在对现有全加器电路研究分析的基础上,提出了一种基于低功耗XOR/XNOR电路和多数决定门的新型高性能全加器电路。多数决定门采用输入电容和静态CMOS反相器实现,降低了电路的功耗,提高了运算速度。采用TSMC 0.18 μm CMOS工艺器件参数,对全加器进行Spectre仿真。结果表明,在2.4 V到0.8 V电源电压范围内,与已有的全加器相比,新全加器在功耗和延迟上都有较大程度的改进。Based on studies and analyses of existing full adders,a novel full adder using XOR/XNOR circuit and majority gate was proposed.The majority gate was composed of input capacitors and static CMOS inverters,which reduced power consumption of the circuit and improved its operational speed.Spectre simulation based on TSMC＇s 0.18 μm process showed that both power consumption and circuit delay of the new full adder were greatly improved in 2.4 V to 0.8 V supply range,compared to the published full adders.

关 键 词：全加器 多数决定门 CMOS 

分 类 号：TN432[电子电信—微电子学与固体电子学]