1.9GHz0.18μm CMOS低噪声放大器的设计  

Design of 1.9 GHz 0.18 μm CMOS Low-Noise Amplifier

作　　者：周建明[1] 陈向东[1] 徐洪波[1] 

机构地区：[1]西南交通大学信息科学与技术学院,四川成都610031

出　　处：《通信技术》2010年第8期76-78,81,共4页Communications Technology

基　　金：教育部新世纪优秀人才支持计划计划支持项目(编号:A0160419950120)

摘　　要：针对1.9GHzPHS和DECT无线接入系统的应用,提出了一种可工作于1.2V电压的基于源级电感负反馈共源共栅结构而改进的CMOS低噪声放大器,并对其电路结构、噪声及线性特性等主要性能进行分析。并与传统的低噪声放大器进行对比,该电路采用两级放大结构,通过加入电容和电感负反馈可以分别实现低功耗约束下的噪声优化和高的线性度。采用TSMC0.18μm CMOS工艺模型设计与验证,实验结果表明:该低噪声放大器能很好满足要求,且具有1.4dB的噪声系数和好的线性度,输入1dB压缩点-7.8dBm,增益11dB,功耗11mW。For the application of 1.9 GHz PHS and DECT wireless access system; a modified CMOS low noise amplifier based on cascode stage structure with a inductor degenerative feedback at common source is proposed, which could operate at 1.2 V supply voltages, and some principal performances, including its circuit structure, noise and linearity, are also analyzed. Contrary to the conventional low-noise amplifier, this circuit, by using two-stage amplifier and adding negative feedback inductor, could achieve noise optimization and high linearity under the constraint of low power consumption. The design is done by using TSMC 0.18 μm CMOS technology, and the experiment results show that the proposed low-noise amplifier could satisfy the requirement, and is of a noise figure of 1.4 dB and good linearity, and with an input-referred 1 dB compression point （IP 1 dB） of-7.8 dBm, the power gain is 11 dB, and the power consumption 11 mW.

关 键 词：低噪声放大器 噪声系数 负反馈 线性度 

分 类 号：TN722.25[电子电信—电路与系统]