低压Rail-to-Rail CMOS运算放大器的设计  

Design of Low-Voltage Rail-to-Rail CMOS Operational Amplifier

作　　者：王永顺[1] 王好德[1] 史琳[1] 

机构地区：[1]兰州交通大学电子与信息工程学院,兰州730070

出　　处：《半导体技术》2010年第8期827-830,共4页Semiconductor Technology

基　　金：甘肃省科技支撑计划项目(097GKCA052)

摘　　要：基于0.5μm标准CMOS工艺,设计了一种带有恒跨导输入级的轨对轨(rail-to-rail)低压CMOS运算放大器。采用折叠式共源共栅差分电流镜放大器输入级和改进的CMOS AB类输出级,实现了电源满幅度的输入输出和恒输入跨导。用Cadence Spectre仿真器,对整个电路在3.3 V工作电压下进行仿真,其直流开环增益AV=70.6 dB,相位裕度PM=71°,单位增益带宽GB=1.37 MHz。芯片面积为0.7 mm×0.4 mm。实际测试结果与模拟结果基本一致。A new rail-to-rail CMOS operational amplifier with low-voltage and constant trans-conductance was designed based on the 0.5 μm standard CMOS technology.The rail-to-rail common mode input range and constant trans-conductance were accomplished using folded-cascode operational amplifier controlled by current mirror and improved output stage based on CMOS class-AB.The simulated results by Cadence Spectre show that the open-loop gain（AV） is 70.6 dB,phase margin（PM） is 71° and unity gain bandwidth（GB） is 1.37 MHz for 3.3 V power supply.The die area is 0.7 mm×0.4 mm,and the test results are basically consistent with the circuit simulation.

关 键 词：运算放大器 低压 恒跨导 轨对轨 折叠式共源共栅 

分 类 号：TN402[电子电信—微电子学与固体电子学]