改进的共享锁存器同步器的设计和应用  

Modified Shared Latch Synchronizer Design and Application

作　　者：冯华星[1] 李晓江[2] 

机构地区：[1]中国科学院微电子研究所,北京100029 [2]杭州中科微电子有限公司,杭州310053

出　　处：《半导体技术》2010年第9期918-922,共5页Semiconductor Technology

基　　金：国家部委基金支持项目

摘　　要：随着设计复杂度的提高,当前SOC系统的集成能力空前提高,SOC的设计面临巨大的挑战。针对多时钟域之间的亚稳态现象,分析了亚稳态产生的原因,介绍了几种同步器的工作原理,比较了各自的优缺点,在此基础上提出了一种改进的共享锁存器同步器。并采用该同步器实现了基于FPGA的GPS基带验证系统中的异步接口设计。验证结果表明,该方法成功实现了不同时钟域之间数据可靠的传输,达到了系统设计的要求。As the increase of design complexity, SOC system can integrate more and more transistors, it brings large challenges to the SOC design. How to keep the stability of data transferring across the multi clock domain, and achieve correctness become the key problems. The reasons causing metastability are analyzed, the operational principles of several synchronizer are introduced, the pros and cons are compared. Based on that a modified shared latch synchronizer was proposed. The shared latch synchronizer was used to realize the. asynchronous interface design of GPS baseband verification system based on FPGA. The verification results show that the shared latch circuit successfully realizes the stable transfer crossing the multi clock domain, and reaches the system design requirements.

关 键 词：多时钟域 亚稳态 同步器 GPS FPGA 验证 

分 类 号：TN79[电子电信—电路与系统]