STI应力对90nm SONOS存储器的影响分析  

Analysis of Influence of STI-induced Stress on 90 nm SONOS Memory

作　　者：徐跃[1] 闫锋[2] 

机构地区：[1]南京邮电大学电子科学与工程学院,江苏南京210046 [2]南京大学电子科学与工程学院,江苏南京210093

出　　处：《南京邮电大学学报（自然科学版）》2010年第4期80-83,89,共5页Journal of Nanjing University of Posts and Telecommunications：Natural Science Edition

摘　　要：随着CMOS工艺按比例缩小到90nm以下,浅沟槽隔离(STI)引起的机械应力对MOSFET器件性能的影响越来越严重。通过实验和TCAD仿真研究了STI应力对一种SONOS结构的90nm非易失存储器的影响。实验和仿真结果表明由于受到STI压应力的作用,靠近STI的SONOS边角存储单元和远离STI的中心存储单元存在阈值电压分布不一致的问题。为了减小STI应力对边角存储单元的影响,分别采用STIrecess和STISi3N4liner两种工艺去减缓STI产生的压应力。TCAD仿真结果表明采用STISi3N4liner工艺后边角存储单元受到的STI压应力比原有的基本工艺降低了20%以上。With CMOS technology scaling down to sub-90 nm,the influence of mechanical stress induced by shallow trench isolation （STI） on MOSFET performances becomes more and more serious. The STI stress on a type of SONOS structures 90 nm non-volatile memory is investigated by experiment and TCAD simulation. The experimental and simulation results have shown that SONOS edge memory cells adjacent to STI have different threshold voltage distribution in comparison with center cells far from STI due to STI compressive stress. To reduce the impact of STI compressive stress on edge cells, STI recess and STI Si3N4 liner technology are introduced to relieve STI-induced stress, respectively. TCAD simulation results demonstrate that in comparison with baseline technology, STI compressive stress is cut down at least 20% with STI Si3 N4 liner technology.

关 键 词：浅沟道隔离 机械应力 非易失存储器 氮化硅衬垫 

分 类 号：TP333.5[自动化与计算机技术—计算机系统结构]