60MHz直接数字频率合成设计与分析  

Designing and Analyzing on 60MHz Direct Digital Frequency Synthesizer

作　　者：范录宏[1] 张玉兴[1] 

机构地区：[1]成都电子科技大学电子工程系

出　　处：《系统工程与电子技术》1999年第7期47-50,共4页Systems Engineering and Electronics

摘　　要：详细介绍了步长为５Ｈｚ的６０ＭＨｚ直接数字频率合成器的设计过程，同时说明了本课题采用锁相环方案实现的难度和缺点，然后结合样机的测试结果，分析了输出信号的频谱分布规律，最后给出了本课题需改进的措施以及ＤＤＳ在雷达中的应用方向。The methods designing about 60MHz,in 5Hz step, direct digital frequency synthesizer (DDS) are introduced in this paper. Meanwhile the difficulties and drawbacks in this project with phase locked loop (PLL) are presented. On the basis of test results, the distribution characteristics of output spectrum are analyzed. In the end, the improved measurements in the project and the prospect about DDS applying to radar are given.

关 键 词：数字式 频率合成器 相位噪声 分辨率 设计 

分 类 号：TN742.102[电子电信—电路与系统]