X-DSP浮点乘法器的设计与实现  

Design and implementation of float point multiplier in X-DSP

作　　者：彭元喜[1] 杨洪杰[1] 谢刚[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073

出　　处：《计算机应用》2010年第11期3121-3125,3133,共6页journal of Computer Applications

基　　金：国家自然科学基金资助项目(60676010);国家863计划项目(2007AA01Z108);教育部长江学者和创新团队发展计划项目

摘　　要：为了满足高性能X-DSP浮点乘法器的性能、功耗、面积要求,研究分析了X型DSP总体结构和浮点乘法器指令特点,采用Booth2编码算法和4∶2压缩树形结构,使用4级流水线结构设计实现了一款高性能低功耗浮点乘法器。使用逻辑综合工具Design Compiler,采用第三方公司0.13μmCMOS工艺库,对所设计的乘法器进行了综合,其结果为工作频率500MHz,面积67529.36μm2,功耗22.3424mW。In order to meet the requirements on performance, power, area of float point multiplier in X-DSP, the architecture of X-DSP was studied, and the characteristics of all the instructions related to its float point multiplier were analyzed. A high-performance and low-power float point multiplier, which used Booth 2 encoding algorithm and 4∶2 compress tree structure and adopt a 4-stage pipeline structure, was designed and implemented. The floating-point multiplier was also synthesized by using design compiler with 0.13 μm CMOS technique of a third-party company. The results show that the frequency is 500 MHz, the area of the circuit is 67529.36 μm2, and the total circuit power consumption is 22.3424 mW.

关 键 词：4∶2压缩树 布斯算法 IEEE-754 浮点乘法器 数字信号处理器 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构] TP342.2[自动化与计算机技术—计算机科学与技术]