A 12 bit 100 MS/s pipelined analog to digital converter without calibration  

作　　者：蔡小波 李福乐 张春 王志华 

机构地区：[1]Institute of Microelectronics,Tsinghua University

出　　处：《Journal of Semiconductors》2010年第11期100-104,共5页半导体学报（英文版）

摘　　要：A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter（ADC） in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC＇s linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumption is 112 mW at a 1.8 V supply,including output drivers.The chip area is 3.51 mm2,including pads.A 1.8 V 12 bit 100 MS/s pipelined analog to digital converter（ADC） in a 0.18μm complementary metal-oxide semiconductor process is presented.The first stage adopts a 3.5 bit structure to relax the capacitor matching requirements.A bootstrapped switch and a scaling down technique are used to improve the ADC＇s linearity and save power dissipation,respectively.With a 15.5 MHz input signal,the ADC achieves 79.8 dB spurious-free dynamic range and 10.5 bit effective number of bits at 100 MS/s.The power consumption is 112 mW at a 1.8 V supply,including output drivers.The chip area is 3.51 mm2,including pads.

关 键 词：pipelined ADC multi-bit OPAMP low power 

分 类 号：TN792[电子电信—电路与系统]