基于AVS标准的熵解码器设计  

Hardware design of variable length decoder based on AVS

作　　者：赵龙辉[1] 陈新华[1] 任怀鲁[1] 

机构地区：[1]山东科技大学,山东青岛266510

出　　处：《微型机与应用》2010年第20期53-55,58,共4页Microcomputer & Its Applications

基　　金：复旦大学专用集成电路与系统国家级重点实验室(09KF007)

摘　　要：阐述了我国拥有自主知识产权的音视频编码技术标准——AVS标准的熵解码算法,介绍了基于AVS标准的熵解码器的设计。根据码流的特点划分硬件模块,采用筒形移位器结构提高解码并行性,应用Verilog硬件描述语言、EDA软件ModelSim仿真、QuartusII软件综合,并通过了Altera公司的Cyclone系列FPGA芯片的下载验证,证明该设计能够实现AVS码流的实时解码功能。This paper discusses the AVS standard which is the audio and video standard that we own independent intellectual property rights and the algorithm of variable length decoder for AVS standard. The design is separated into several parts according to the specialty of the code flow;Barrel shifter and other structures are used to improve decoding parallelism; The design has been implemented with Verilog HDL,Simulated using modelsim software,compilated using quatrusII software and verified by Altera＇s Cyclone series FPGA. The realized system can decode the AVS video in real-time.

关 键 词：AVS 熵解码 可编程逻辑门阵列 VERILOG硬件描述语言 

分 类 号：TN919.8[电子电信—通信与信息系统]