一种低功耗异步FIFO在ASIC中的设计  

A Design of Low-Power Consumption Asynchronous FIFO in ASIC

作　　者：范小虎[1] 杨波[1] 孙涛[1] 

机构地区：[1]济南大学信息科学与工程学院,山东济南250022

出　　处：《济南大学学报（自然科学版）》2011年第1期1-5,共5页Journal of University of Jinan(Science and Technology)

基　　金：国家自然科学基金(60903176);山东省自然科学杰出青年基金(JQ200820);山东省信息产业发展专项(2008R00039);济南市企业自主创新计划专项(200807010)

摘　　要：为解决PCI视频采集卡中跨时钟域数据准确传输的问题,提出一种低功耗的异步先进先出(First In First Out,FIFO)存储器模块的实现方案。为适应大量的视频数据猝发传输设计一种宽为36位、深为256的异步FIFO,基于低功耗设计思想,使用格雷码地址编码以有效抑制亚稳态,增加了门控时钟电路。该模块已经过测试验证,并与音视频模块和PCI桥集成后流片,可以工作在最大197 MHz的频率下,完全符合设计要求。该桥芯片可以支持4路D1画质(704×576分辨率)实时音视频数据稳定采集。Facing the data accurate transmission problem of cross clock domain in the video capture card through PCI interface, we proposed a low-power consumption asynchronous FIFO memory module, which has a width of 36bits and a depth of 256 to carter the large amount video data demand of burst transfer. Complying with the low-power consumption design strategy, we encoded the address pointer using Gray code to inhibit the metastable state effectively,and a clock gating circuit was added into our design. The module has been tested and verified, and can maximally work at 197 MHz frequency after integrated with PCI bridge audio ＆ video module and taped out. This multimedia bridge ASIC can support up to 4 channels D1 quality （704 ×576 resolution） real-time audio and video data stable collection.

关 键 词：专用集成电路(ASIC) 异步FIFO 格雷码 低功耗 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]