数模混合片上系统模拟芯核并行测试结构  

Research on Test Structure of Analog Cores in Mixed-Signal SoCs

作　　者：靳洋[1] 王红[1] 杨士元[1] 吕政良[1] 郑焱[1] 

机构地区：[1]清华大学自动化系,北京100084

出　　处：《计算机辅助设计与图形学学报》2010年第11期2004-2012,共9页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(60633060;60773142);国家"九七三"重点基础研究发展规划项目(2005CB321604);教育部博士点专项基金资助项目(20070003122)

摘　　要：为了减少测试成本,基于片上数字化的思想,提出复用片上DAC和ADC数模混合片上系统模拟芯核并行测试结构.自保持模拟测试接口可暂存模拟测试激励和测试响应,减少每个测试端口添加的DAC和ADC所产生的额外面积开销,实现芯核级多端口测试和系统级的多核并行测试.采用流水线式并行测试结构减少DAC输出测试激励的等待时间;并进一步分析了模拟测试外壳的测试成本评价方法和优化问题数学模型,在此基础上设计测试成本优化算法,得到优化的模拟测试外壳组分配方案.实验结果表明,文中提出的模拟芯核测试结构对精度的影响小于0.25%,对测试时间可优化40%以上.To reduce the huge test cost,based on on-chip virtual digitization method,a parallel test structure for analog cores in mixed-signal SoCs,which using on-chip DAC and ADC,is proposed.The proposed self-hold analog test interface（SHATI）can realize temporal storage of analog test stimuli and test responses,which eliminates the extra silicon overhead caused by DAC and ADC on each test port and enables core-level and system-level parallel test for analog cores.The pipelined parallel test structure can further reduce the waiting time of test stimuli application.Test cost of analog cores is then analyzed and its optimization model is established.Optimized test wrapper groups with minimized test cost can be obtained by proposed optimization algorithm.The experimental results show that the test accuracy error with the proposed test structure is under 0.25% and test time is optimized by 40%.

关 键 词：数模混合片上系统 模拟芯核 自保持模拟测试接口 流水线式并行测试 测试成本 

分 类 号：TP[自动化与计算机技术]