流水线处理器中Cache模块的设计  

Design of the Cache in the Pipeline Processor

作　　者：李红桥[1] 肖建青[1] 张洵颖[1] 龚龙庆[1] 

机构地区：[1]西安微电子技术研究所,西安710054

出　　处：《科学技术与工程》2010年第32期8084-8089,共6页Science Technology and Engineering

摘　　要：流水线结构能大幅提高指令执行速度,但是由于主存读取速度过慢,系统性能的提升仍然受到限制。现实现的Cache设计,是流水线与主存间的高速缓冲器,它能有效地解决访存的瓶颈问题,使流水线功能得到充分发挥。文章首先分析流水线的结构特点,确定Cache的结构功能,在此基础上提出一个组相联映射Cache的设计。分析Cache实现读写操作的具体控制过程,并给出LRU(least recently used)替换算法的实现。最后通过介绍猝发取指操作着重讨论了Cache与流水线间的配合机制。The pipeline could increasing the speed of executing instructions greatly,but the processor performance were still subjected to the time of accessing main memory. The cache described is a high speed buffer between the pipeline processor and main memory,it can break the bottleneck ,bringing the pipeline into full play. Firstly,the organization of the pipeline to determine the architecture of the cache is analyzad,then a design of a set-associative cache is present,describing the operation of writing and reading,the realization of LRU algorithm. Lastly,how the pipeline processor and cache coordinate with each other by introducing the burst fillare Discussed.

关 键 词：流水线 组相联 LRU替换算法 猝发取指 

分 类 号：TP393.06[自动化与计算机技术—计算机应用技术]