Nios-Ⅱ下的Lvds高速串行接口IP设计与实现  

IP Design and Realization of Lvds High-speed Serial Interface Based on Nios-Ⅱ

作　　者：胡胜[1] 宋跃[1] 雷瑞庭[1] 李君[1] 

机构地区：[1]东莞理工学院,广东东莞523808

出　　处：《仪表技术与传感器》2010年第10期54-56,110,共4页Instrument Technique and Sensor

基　　金：国家自然科学重大基金项目(10890095);东莞市2006年科技计划项目(第2批序号11)

摘　　要：介绍了Nios-Ⅱ处理器的外设IP的设计方法,详细介绍了一种可用于多片FPGA板间通信的自定义高速串行接口IP的设计,该IP采用主、从结构,使用Lvds接口进行底层串行数据的高速传输,同时给出了相关的驱动程序的编写方法。实验表明,该IP可被无缝整合到各种形式的SOPC嵌入式系统中。The design method of the peripheral IP based on Nios-Ⅱ processor was introduced.IP design of high-speed serial interface in master-slave structure was introduced in detail,which could be used in communication in more pieces of FPGA board,in which Lvds interface was used for high-speed serial data transmission in bottom layer.The driver＇s writing method was also given.Experiments showed that this IP could be seamlessly integrated into various forms of the SOPC embedded systems.

关 键 词：Nios-Ⅱ IP设计 串行数据接口 LVDS FPGA/SOPC Verilog 

分 类 号：TP274[自动化与计算机技术—检测技术与自动化装置]