一种高线性度CMOS自举采样开关  

A High Linearity CMOS Bootstrapped Sampling Switch

作　　者：潘小敏[1] 黄言平[2] 陈珍海[3] 

机构地区：[1]无锡市商业职业技术学院,江苏无锡214153 [2]北京华航无线电测量研究所,北京100013 [3]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2010年第11期29-32,35,共5页Electronics & Packaging

摘　　要：作为ADC系统与外界的接口,采样开关的性能优劣直接决定了ADC所接收到的信号纯度和真实性。高线性度的CMOS开关可在极大程度上抑制采样时间不确定、时钟馈通和电荷注入等非线性误差。文章首先讨论了MOS采样开关非线性的来源和互补型CMOS采样开关的不足之处,然后设计实现了一种高线性度CMOS自举采样开关。仿真结果表明所设计的高线性度CMOS自举开关的SFDR达101.5dB,可以适用于16位精度的ADC应用要求。Sampling switch is the front-end of ADC. The performance of sampling switch affected the signal purity of the sampled analog signal directly. The nonlinearities such as sample clock jitter, clock feed through and charge injection of the sampling switch can be rejected greatly by a high linearity CMOS sampling switch. Firstly, the nonlinearity source of MOS sampling switch and the disadvantage of complemented CMOS sam- piing switch is discussed. Secondly, a simple high linearity CMOS bootstrapped sampling switch is designed. The simulation results indicate the SFDR of the designed high linearity CMOS sampling switch is 101.5dB, meeting the requirement of 16-bit ADC.

关 键 词：模数转换器 采样开关 线性度 自举开关 

分 类 号：TN402[电子电信—微电子学与固体电子学]