一种异构多核片上系统的SystemC系统级综合方法  

SystemC system level synthesis method for heterogeneous MPSoC

作　　者：冯志华[1,2] 陈曦[3] 高社生[1] 

机构地区：[1]西北工业大学自动化学院,陕西西安710072 [2]北京计算机技术及应用研究所,北京100854 [3]清华大学电子工程系,北京100084

出　　处：《系统工程与电子技术》2010年第11期2484-2488,共5页Systems Engineering and Electronics

摘　　要：针对传统集成电路综合方法的不足,提出了一种异构多核片上系统的SystemC系统级综合方法。阐述了系统级综合的SystemC非定时设计输入模型,给出了多核控制器做复杂控制和算法IP做运算加速的目标片上系统架构及综合流程。在此基础上开发了SystemC系统级综合集成开发环境,并进行了通信处理异构多核片上系统的设计和实现。实验结果表明,该方法有效地提高了软硬件混合片上系统的设计效率,缩短了研制周期。Aiming at the shortcoming of the traditional large scale integrated circuit synthesis method,a novel SystemC electronic system level synthesis（SLS） method is proposed.The heterogeneous multiprocessor system on a chip（MPSoC） hardware architecture which is the target for a system level synthesis system and a SLS synthesis flow are described.The SLS method supports a SystemC untimed model as its design entry and adopts the target MPSoC hardware architecture that has a multiprocessor as the controller and algorithmic IPs as computation accelerators.Furthermore,a system level synthesis integrated development environment（IDE） is implemented,and a MPSoC processor is developed with the IDE.Experimental results show that the proposed synthesis method improves the efficiency of software/hardware mixed MPSoC systems effectively and reduces the time put on the market.

关 键 词：大规模集成电路 SYSTEMC 系统级综合 体系结构 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]