一种基于优化IP核的数字中频接收机  

A Digital IF Receiver based on Optimized IP Core

作　　者：赵兵[1] 徐家品[1] 

机构地区：[1]四川大学电子信息学院,四川成都610065

出　　处：《通信技术》2010年第11期6-8,共3页Communications Technology

摘　　要：随着现场可编程门阵列(FPGA)的出现,基于软件无线电的数字中频技术目前被广泛地应用到3G基站中。结合多速率信号处理理论,采用分级实现的方法对码分多址扩频复用(WCDMA)基站中的数字中频接收系统进行优化设计,提出一种基于FPGA硬件的IP核实现方案。仿真结果表明,IP核简洁的图形化界面保证设计可靠性的同时优化了硬件资源的配置,极大地减少了计算量进而显著缩短了设计时间。With the emergence of field programmable gate arrays（FPGA）,digital intermediate-frequency technology based on software-defined radio is widely used in 3G base stations.With the multirate of signal processing theory,the digital IF receiver of WCDMA system is optimized by hierarchical implementation,and then a scheme based on IP core of FPGA is proposed.The simulation result shows that clear graphical interface of IP core could ensure the reliability of design and optimize the hardware resources,while greatly reduces the amount of calculation and thus significantly shortening the design cycle.

关 键 词：数字下变频 数控振荡器 IP核 积分梳状滤波器 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]