一种低功耗高稳定性晶体振荡器芯片的设计  

Design of Crystal Oscillator Chip with Low Power and High Stability

作　　者：陈红梅[1] 徐静平[1] 钟德刚[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《微电子学与计算机》2010年第12期105-108,共4页Microelectronics & Computer

基　　金：国家自然科学基金项目(60776016)

摘　　要：分析了传统Pierce振荡器不足,提出了改进型的振荡器结构,并基于0.35μm CMOS工艺,设计实现了一款低功耗高稳定性的晶体振荡器芯片.芯片有两种工作模式:正常工作模式和低功耗模式.测试结果表明,在电源电压为5 V、振荡频率为30 MHz、负载电容15 pF时,芯片消耗总电流低于5 mA,振荡电路消耗电流仅为0.6 mA,输出占空比为50±0.8%的方波信号,其频率随电源电压的变化率仅为0.5×10-6.引入低功耗模式,振荡器消耗电流降低至3μA以下,和传统结构相比,功耗降低了60%,频率随电压稳定性提高了10倍.A crystal oscillator chip with low power and high stability is presented.On the basis of analyzing the disadvantages of the conventional Pierce crystal oscillator,a novel crystal oscillator structure has been proposed.The chip can work under two modes： normal operating mode and power-dissipation mode.Based on 0.35 μm CMOS process,the test results show that total consumption of the chip is less than 5 mA with power supply voltage of 5 V,oscillation frequency of 30 MHz,load capacitance of 15 pF,and the oscillator circuit is only 0.6 mA,output square wave signal with duty cycle of 50 ± 0.8%,frequency stability 0.5×10-6.By introducing the power-dissipation mode,current consumption of the oscillation circuit is dropped to 3 μA.Compared with the conventional structure,the power-dissipation has been reduced 60%,frequency stability raised ten times.

关 键 词：Pierce晶体振荡器 低功耗 高稳定性 CMOS工艺 

分 类 号：TN432[电子电信—微电子学与固体电子学]