32位MIPS处理器可测性设计与实现  

Design for Testability of a 32-Bit MIPS Processor and Its Implementation

作　　者：周妮[1] 乔飞[1] 谭斯斯[1] 李常[1] 杨华中[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《微电子学》2010年第6期782-786,791,共6页Microelectronics

基　　金：国家自然科学基金资助项目(60871005);教育部博士点基金(新教师基金)资助项目(200800031073)

摘　　要：设计了一个32位MIPS处理器。为实现负载均衡和提高系统利用率,采用自定义的5级流水线结构,并采用数据旁路机制和基于历史的分支预测机制来解决流水线冲突。同时,为保证芯片设计的可靠性和可测性,采用流水线分级验证的可测性设计方法,在设计中提取流水阶段的关键信号作为输出。为减小芯片面积和管脚数目,设计了多模式的工作机制,实现了芯片管脚复用。后仿结果表明,基于0.18μm CMOS工艺,处理器可工作于60 MHz频率。芯片核心面积为1.15 mm×2.25 mm,等效门为13.5万,功耗为2.8 mW/MHz。测试结果表明,芯片可在多工作模式之间正常切换,功能完整。A 32-hit MIPS processor was presented. To realize load balance and increase system efficiency, a custom five-stage pipeline structure was employed. Furthermore, data bypass and branch prediction based on history records were adopted to solve hazards of pipelined processor. In order to ensure reliability and testability, stage decomposition checking was used. Key signals of the pipeline stages were extracted as output signals. Meanwhile, multiple modes were proposed and reusing of pads were achieved to reduce chip area and number of pads. Post-layout simulation based on 0. 18μm CMOS technology indicated that the processor had a maximum frequency of 60 MHz. Having 135 k gates, the core circuit occupies a chip area of 1.15 mm×2.25mm. With a total power con sumption of 2, 8 mW/MHz, the processor functions perfectly and switches properly between multiple modes.

关 键 词：MIPS处理器 数据旁路 分支预测 可测性设计 

分 类 号：TN402[电子电信—微电子学与固体电子学]