433MHz ASK接收机中低噪声锁相环的设计  

Design of Low Phase Noise PLL for 433MHz ASK Receiver

作　　者：许帅[1] 何伟[1] 张润曦[1] 马聪[1] 赖宗声[1,2] 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062 [2]华东师范大学纳光电集成与先进装备教育部工程研究中心,上海200062

出　　处：《微电子学》2010年第6期805-809,共5页Microelectronics

基　　金：国家科技重大专项基金资助项目(2009ZX01034-002-002-001-02)

摘　　要：采用0.18μm CMOS RF工艺,实现了一款用于433 MHz ASK接收机的低噪声锁相环。系统采用优化的电源组合和合理的版图布局避免模块间的噪声干扰;VCO模块运用LC滤波器、LDO调压器,结合开关电容阵列调谐技术,提高相位噪声性能;针对鉴频鉴相器和电荷泵的非线性问题进行详细讨论和优化,提高了线性度。测试结果表明,电源电压为3.3 V时,偏置电流为7 mA,中心频率为433 MHz,在频偏100 kHz和1 MHz处,相位噪声分别-为96.47 dBc/Hz和-126.96 dBc/Hz。A low phase noise PLL for 433 MHz ASK receiver was fabricated in 0.18 μm CMOS RF process.In this circuit,power supply configuration and layout were optimized to reduce noise coupling.LC filters,LDO regulator and digitally controlled switched capacitor array were implemented to increase phase noise performance of the VCO.Nonlinearity of phase/frequency detector and charge-pump was discussed for optimization and improvement of linearity.Measurement results showed that the PLL achieved a phase noise of-96.47 dBc/Hz and-126.96 dBc/Hz at 100 kHz and 1 MHz offset from the center frequency of 433 MHz,respectively,while drawing 7 mA of power from a 3.3 V supply.

关 键 词：CMOS 接收机 锁相环 相位噪声 

分 类 号：TN432[电子电信—微电子学与固体电子学]