一种新型差分脉宽控制环路的设计  

Design of a New Differential Pulse Width Control Loop

作　　者：周仕波[1,2] 王永禄[2] 朱灿[2] 

机构地区：[1]重庆邮电大学,重庆400065 [2]模拟集成电路重点实验室,重庆400060

出　　处：《微电子学》2010年第6期861-864,879,共5页Microelectronics

摘　　要：设计了一种新型时钟稳定电路—差分脉宽控制电路。用参考电路产生参考电压,避免因采用环形振荡器等方法产生大的时钟抖动。同时,在控制电路部分用交叉耦合正反馈来调节时钟占空比。该电路采用0.18μm工艺,电源电压为1.9 V,输入时钟占空比调节范围为25%~75%,时钟频率为2 GHz,时钟抖动小于200 fs。A differential pulse width control loop was designed,which is a novel clock stabilizer.In this circuit,reference voltage was generated by a reference circuit to avoid big clock jitter caused by conventional method using ring oscillator.Also,cross-coupled positive feedback was adopted in the control circuit to adjust clock duty cycle.Fabricated in 0.18 μm process technology,the proposed circuit has a supply voltage of 1.9 V,a duty cycle tuning range of input clock from 25% to 75%,a clock frequency of 2 GHz,and a clock jitter less than 200 fs.

关 键 词：时钟稳定电路 差分脉宽调整电路 占空比调节范围 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]