一种基于并行处理器的快速车道线检测系统及FPGA实现  

A Fast Traffic Lane Detection System Based on Parallel Processors and FPGA Implementation

作　　者：李元金[1] 张万成[1] 吴南健[1] 

机构地区：[1]中国科学院半导体研究所,北京100083

出　　处：《电子与信息学报》2010年第12期2901-2906,共6页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(60976023)资助课题

摘　　要：该文提出了一种并行的快速车道线检测系统。该系统包含一个32×32的处理器单元(PE)阵列和双RISC子系统。PE阵列实现车道线图像像素级并行预处理,获取图像边缘特征,双RISC核子系统根据边缘特征实现两条车道线直线参数的并行检测,从而使得检测过程的每一步都是并行进行,显著提高检测速率。该系统用FPGA实现。实验结果表明本系统具有良好的鲁棒性且可达到每秒50帧的检测速率,满足了车道偏离预警系统实时性要求,具备重要的应用价值。This paper proposes a parallel fast traffic lane detection system. The system consists of a 32×32 Processing Elements （PE） array and a dual RISC core subsystem. The PE array performs pixel-parallel image preprocessing and outputs edge features, the dual RISC core subsystem performs two lanes parameters detection in parallel based on edge features. In this way, every step in the detection process is in parallel and the detection rate is rapidly increased. The system is implemented with FPGA. The experiment shows that it has good robustness and can reach up to 50 fps. This meets the demand of real-time for lane departure warning system and makes an important sense for practical application.

关 键 词：图像处理 车道线检测 并行 FPGA 精简指令集计算机(RISC) 

分 类 号：TP391.41[自动化与计算机技术—计算机应用技术] TN432[自动化与计算机技术—计算机科学与技术]